A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word line plates, control gate plates) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such electrical connections includes forming a so-called “stair step” structure at edges of the tiers of conductive structures. The stair step structure includes individual “steps” defining contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures.
As vertical memory array technology has advanced, additional memory density has been provided by forming vertical memory arrays to include additional tiers of conductive structures, and, hence, additional steps in the stair step structures associated therewith. A conventional process of forming a stair step structure may include repeated acts of trimming a uniform width of a mask (e.g., photoresist) overlying alternating conductive structures and insulating (e.g., dielectric) structures, etching portions of the insulating structures not covered by a remaining portion of the mask, and then etching portions of the conductive structures not covered by remaining portions of the insulating structures. As the number of memory cells in such vertical memory arrays increases, such as by increasing the number of memory cells in vertical strings of the vertical memory arrays, a depth (i.e., a height) of the stair step structure increases. In other words, the distance between, for example, a lowermost step and an uppermost step may increase as the number of memory cells in the vertical memory array increases. In addition, as the number of steps increases, a distance between facing regions of the stair step structure may exhibit a similar increase.
The increase in depth of the stair step structures and the increase in the distance between adjacent, facing regions of the stair step structure present problems in filling such regions with insulative materials. For example, chemical mechanical planarization of insulative materials located between adjacent regions of the stair step structure often undesirably removes portions of uppermost tiers of the stair step structure, such as of conductive word lines of the uppermost tiers. Damage to the conductive word lines may result in a damaged electrical connection between a conductive word line and memory cells intended to be electrically coupled to that conductive word line. If the damage to the conductive word lines is excessive enough, the vertical memory array may not work for its intended purpose and may fail, requiring scrapping of the semiconductor device including the vertical memory array.